1. Field of the Invention
The present invention relates to the High Definition Multimedia Interface (HDMI) operation, and specifically to the automatic PLL (phase locked loop) control to lock to the input reference clock over a wide frequency range.
2. Prior Art
Any High Definition Multimedia Interface (HDMI) receiver must support an input reference clock frequency range of 25 MHz to 165 MHz. The input can be within this frequency range without providing prior knowledge to the receiver. It is necessary for the receiver to provide a PLL that can lock to the input clock frequency and generate the required output frequencies.
It has not been possible to operate a single PLL over this very wide frequency range in the past. Typically it cannot be done with a single prior art PLL design, as it is difficult to have such a wide frequency range in a tuned load circuit with the necessary gain. Since it is difficult to design a PLL which can generate such a large output clock frequency range, it has been necessary to use multiple PLLs to cover the required range, with each PLL in the group covering a portion of the required range.
A typical prior art PLL uses a frequency and phase comparator to provide input to a charge pump which generates an analog voltage output that is used to control the VCO frequency within the range of the tunable load. This generated frequency is expected to be an estimate of the input frequency which is lockable within the bandwidth of the PLL load used. Since the tuning range of each PLL is relatively small, the prior art uses multiple PLLs with overlapping frequency ranges to cover the total required frequency range of HDMI. This is silicon area consuming, and costly. It also results in higher power consumption as PLLs have to be enabled to ensure coverage of frequency as well as a continuous lock.
FIG. 1 is a block diagram 100 of a typical prior art PLL implementation. The PLL comprises an input block for Frequency and Phase Sensing (FPS) 110, which typically comprises a phase and frequency detector and comparator (PFD) block 111 and a low pass filter (LPF) block 112, as shown. The output of FPS 110 is used to control a charge pump 120 having a voltage output that varies with the phase difference between the incoming reference frequency and a feedback frequency. Typically the reference frequency is a fraction of the needed output frequency ‘F’ by a factor ‘N’ (Ref freq=F/N where ‘F’ is the output frequency required and ‘N’ is an integer). The generated charge pump 120 voltage, in turn, controls a voltage controlled oscillator (VCO) 130. The VCO output is fed back to the PFD 111 through a frequency divider 140, which converts it to the lower frequency F/N. The frequency and phase of this feedback is compared with the frequency and phase of the reference frequency to achieve a lock when the PLL is operational. The VCO frequency can be varied within a small range to achieve the necessary frequency lock of the PLL. This range is limited by the gain and bandwidth of the load of the VCO.
In view of the limitations of the prior art, it would be therefore beneficial to provide a single PLL that would have a wide frequency range of operation, i.e., be able to lock on a wide range of input frequencies. It would be further advantageous if such wide range of frequencies would be suitable for operation over the HDMI frequency range using a single PLL.